Conventionally, micromechanical sensor elements having diaphragms are used for relative pressure measurement. For this use, the diaphragm, which is usually formed in the upper surface of the component, must be accessible on both sides. In practice, the diaphragm of such micromechanical sensor elements is therefore frequently exposed from the back side of the wafer. Bulk micromechanical methods are used for this, such as KOH etching, relatively large openings developing, which codetermine the size of the sensor elements.
German Patent Application Nos. DE 100 32 579 A1, DE 10 2004 036 035 A1, and DE 10 2004 036 032 A1 describe methods that are also known as APSM (advanced porous silicon membrane) technology. These methods may be used to produce sensor elements for absolute pressure measurement having a very small chip surface and very exact production tolerances, for example. These methods may be implemented in a relatively simple manner and are accordingly cost-effective. Since the APSM technology is also CMOS compatible, circuit elements of an evaluation circuit and in particular resistors for the piezoresistive signal detection are able to be simply integrated into the sensor element.
In the method described in German Patent Application No. DE 100 32 579 A1, an etching medium that attacks the unmasked upper surface regions of a monolithic silicon substrate is used to produce a first porous layer region in the substrate, which layer borders the upper surface of the substrate. The rate of expansion of the pores may be influenced by the application of an electric field between the top side and the bottom side of the substrate and by suitable adjustment of the electric field strength during the etching attack. An increase in the electric field strength produces beneath the first layer region a second porous layer region, whose porosity is greater than the porosity of the first layer region. In a subsequent annealing step, the pores rearrange themselves in the second layer region such that a single large pore, i.e., a cavity, forms beneath the first layer region. At least the pores on the top side of the first layer region are largely closed by the annealing. Thus, it is possible to deposit a substantially monocrystalline silicon layer as a diaphragm layer on this first layer region, into which electric circuit elements, such as resistors, for example, may be integrated simply for signal detection and evaluation.
In the methods described in German Patent Application Nos. DE 10 2004 036 035 A1 and DE 10 2004 036 032 A1, a first region having a first doping is produced in a semiconductor substrate, which region is to form the cavity under the diaphragm to be produced. Above this first region, a latticed region having a second doping is produced, which acts as a stabilization element for the diaphragm to be produced. In a first method variant, the first region is then rendered highly porous by etching through the lattice openings of the stabilization element. As a result of the different dopings, the stabilization element is practically not attacked in the process. Afterward, the semiconductor substrate is provided with an epitaxy layer. This grows generally on the lattice structure of the stabilization element, the growth occurring both in the vertical and in the lateral direction, so that the lattice openings close. During the growth process or during an annealing step, the highly porous semiconductor material of the first region deposits to form a large pore or a cavity beneath the ideally monocrystalline epitaxy layer, which then acts as a diaphragm layer. In a second method variant, the semiconductor material of the first region is completely dissolved out even before the production of the epitaxy layer.
Since in this case, subject to the process, the diaphragm layers bordering the cavity often are made up of the same material as the substrate, to with of monocrystalline silicon, a subsequent patterning of the back side of the substrate to produce an access opening to the cavity proves problematic. In this case, particular measures for protecting the diaphragm structure are necessary.
U.S. Patent Application No. 2006/0260408 A1 concerns itself with this problem. Among other things, it proposes to restrict temporally the etching attack from the back side of the substrate, namely such that an access opening to the cavity is produced, but the above-lying diaphragm structure is not attacked to the greatest extent possible.
In practice, it has been shown that such a temporal restriction of the etching attack on the back side is critical and therefore is not readily suitable for mass production. One reason for this is that the thickness of the diaphragm structure and the dimensions of the cavity are slight compared to the thickness of the substrate. In addition, the thickness of the diaphragm structure falls within the range of the thickness variations with which the wafers normally used as a substrate material are produced. On the whole, the temporal restriction of the etching attack on the back side is therefore very delicate.